Supported Communication Protocols#
Mooncake Transfer Engine supports multiple communication protocols for data transfer between nodes in a cluster. The protocol selection depends on your hardware capabilities and performance requirements.
Quick Reference#
Protocol |
Hardware Required |
Use Case |
Python API Support |
|---|---|---|---|
tcp |
Standard network |
General purpose, works everywhere |
✅ Primary |
rdma |
RDMA-capable NIC |
High-performance, low-latency |
✅ Primary |
efa |
AWS EFA-capable instance |
High-performance on AWS (libfabric SRD) |
✅ Primary |
nvmeof |
NVMe-oF capable storage |
Direct NVMe storage access |
⚠️ Advanced |
nvlink |
NVIDIA MNNVL |
Inter-node GPU communication |
⚠️ Advanced |
musa |
Moore Threads GPU + MTLink |
Intra-node GPU IPC/P2P |
⚠️ Advanced |
nvlink_intra |
NVIDIA NVLink |
Intra-node GPU communication |
⚠️ Advanced |
hip |
AMD ROCm/HIP |
AMD GPU communication |
⚠️ Advanced |
barex |
RDMA-capable NIC |
Bare-metal RDMA extension |
⚠️ Advanced |
cxl |
CXL-capable hardware |
Memory pooling and sharing |
⚠️ Advanced |
shm |
None (POSIX shm, same host) |
Same-host DRAM copies without NIC loopback |
⚠️ Advanced |
ascend |
Huawei Ascend NPU |
Ascend NPU communication |
⚠️ Advanced |
hylink |
Hygon DCU + DTK |
Hygon DCU HSL fabric communication |
⚠️ Advanced |
tpu |
Google TPU (PJRT) |
TPU KV-cache transfer via host-DRAM staging |
🧪 Experimental (TENT) |
xpu |
Intel GPU + oneAPI SYCL |
Host staging and same-node XPU P2P/IPC; TCP/RDMA between nodes |
⚠️ Advanced (TENT) |
mpcomm |
RDMA-capable NIC(s) |
Multi-NIC memory pooling with NIC/QP load balancing |
⚠️ Advanced (TENT) |
flagcx |
RDMA-capable NIC(s) |
Unified P2P transfer through FlagOS FlagCX |
⚠️ Advanced |
Commonly Used Protocols (Python API)#
TCP (Default)#
Description: Standard TCP/IP network protocol.
Use When:
No special hardware is available
Testing or development environments
Compatibility is more important than performance
Configuration:
# Python API
engine.initialize(
hostname="localhost",
metadata_server="P2PHANDSHAKE",
protocol="tcp", # No device_name needed
device_name=""
)
# Environment variables
export MOONCAKE_PROTOCOL="tcp"
Advantages:
Works in all environments
No special hardware required
Simple setup
Limitations:
Lower throughput compared to RDMA
Higher CPU overhead
Higher latency
RDMA (Recommended for Production)#
Description: Remote Direct Memory Access protocol providing high-performance, low-latency data transfer with minimal CPU overhead. Supports accelerator-aware memory registration, including NVIDIA GPUDirect RDMA for CUDA buffers and Cambricon MLU buffers when built with Neuware.
Hardware Support:
InfiniBand
RoCE (RDMA over Converged Ethernet)
eRDMA (Elastic RDMA)
NVIDIA GPUDirect RDMA
Non-NVIDAI GPUDirect RDMA (e.g., Intel E810 RDMA NIC)
Cambricon MLU memory via Neuware (
-DUSE_MLU=ON)Biren GPU memory via SUPA (
-DUSE_SUPA=ON)Intel XPU memory via dma-buf (
-DUSE_XPU=ON -DUSE_TENT=ON)
Use When:
High-performance networking is required
RDMA-capable NICs are available
Low latency is critical (e.g., distributed inference, KV cache transfer)
Note: If no RDMA HCA (Host Channel Adapter) is detected on the system, the Transfer Engine will automatically fall back to TCP protocol for compatibility.
MLU Note: Cambricon MLU support uses the standard rdma data path. There is no separate mlu protocol string. To enable MLU memory detection, topology discovery, and DMA-BUF based registration, build Transfer Engine with -DUSE_MLU=ON and make Neuware available through NEUWARE_HOME or NEUWARE_ROOT.
Intel XPU Note: Intel XPU support lives in TENT (-DUSE_XPU=ON -DUSE_TENT=ON, run with MC_USE_TENT=1). On registration, VRAM is exported through Level Zero as a dma-buf and registered with ibv_reg_dmabuf_mr, so RDMA reads and writes go to VRAM directly. The direct path is per buffer, not guaranteed: when the NIC or rdma-core lacks dma-buf support, when the export fails for an allocation (for example small foreign USM allocations pooled by the Intel compute runtime, see the build guide), or when transports/rdma/disable_gpu_direct_rdma is true, the engine transparently stages that VRAM through pinned host memory over the same RDMA or TCP transport. A request hinted to another transport (e.g. tcp), or one whose selector policy only admits a DRAM-only transport (e.g. hp_tcp), is staged as well. Within one process, VRAM-to-VRAM copies between two XPUs on the same node go directly over PCIe (or Xe Link) when the devices have peer access, and are bounced through host memory otherwise. Across processes on the same node (for example a prefill and a decode worker), registered VRAM is also published with a Level Zero IPC handle; the peer maps it into its own context and the copy runs as a local XPU copy instead of going through the network transport. Opening a peer’s handle fetches its dma-buf descriptor with pidfd_getfd(2), which needs ptrace permission over the exporting process: the Level Zero runtime marks its processes PR_SET_PTRACER_ANY, so the same user in the same PID namespace suffices under Yama ptrace_scope 0 or 1, while ptrace_scope 2 needs CAP_SYS_PTRACE; when that is refused, or when transports/xpu/disable_ipc is true, the engine falls back to the network path.
XPU initiator requirement: Both direct RDMA and host-staged transfers involving XPU memory currently require an XPU-platform initiator. Staging additionally requires its XpuTransport to be enabled; without it, XPU memory is not staged and is routed only over a transport that copies device memory itself, such as TCP. A CPU-platform initiator is not supported even when its local buffer is DRAM and only the remote buffer is XPU memory; it cannot transparently fall back to staging. A cpu:0 buffer in an XPU-platform process does not exercise this CPU-platform case. Foreign/fallback USM whose dma-buf size exceeds its allocation size is conservatively staged, including ambiguous padding; see the build guide.
Configuration:
# Python API - With specific device
engine.initialize(
hostname="node1",
metadata_server="etcd://10.0.0.1:2379",
protocol="rdma",
device_name="mlx5_0" # Specify your RDMA device
)
# Python API - With auto-discovery
engine.initialize(
hostname="node1",
metadata_server="P2PHANDSHAKE",
protocol="rdma",
device_name="auto-discovery" # Automatically detect optimal device
)
# Environment variables
export MOONCAKE_PROTOCOL="rdma"
export MOONCAKE_DEVICE="mlx5_0" # or "auto-discovery"
Device Discovery: To find available RDMA devices on your system:
ibv_devices # List InfiniBand/RDMA devices
# Example output: mlx5_0, mlx5_1, erdma_0, etc.
Advantages:
Very high throughput (up to 200 Gbps per NIC)
Ultra-low latency (sub-microsecond)
Minimal CPU overhead
Supports GPUDirect RDMA for zero-copy GPU transfers
Multi-NIC bandwidth aggregation
Topology-aware path selection
Limitations:
Requires RDMA-capable hardware
May require elevated permissions (sudo)
More complex network configuration
Performance Tips:
Use multiple RDMA NICs for bandwidth aggregation
Enable GPUDirect RDMA for GPU memory transfers
Configure proper NUMA affinity for optimal performance
See Transfer Engine Benchmark Tuning for detailed optimization
EFA (AWS Elastic Fabric Adapter)#
Description: AWS EFA transport using libfabric’s Scalable Reliable Datagram (SRD) protocol, providing high-bandwidth RDMA-like performance on AWS instances without traditional RDMA support.
Use When:
Running on AWS EFA-enabled instances (e.g., p5e.48xlarge, p6-b200.48xlarge, p4d.24xlarge)
High-performance networking is required on AWS
Traditional RDMA (ibverbs QP) is not supported by the hardware
Configuration:
# Python API
engine.initialize(
hostname="localhost",
metadata_server="P2PHANDSHAKE",
protocol="efa",
device_name=""
)
Build Requirements:
cmake .. -DUSE_EFA=ON -DUSE_CUDA=ON
Note:
-DUSE_CUDA=ONis required when transferring GPU memory. Without it, fallback to TCP protocol will fail with “Bad address” errors on GPU buffers.
Advantages:
High throughput (~170 GB/s with 8 EFA devices, tuned)
Bypasses kernel network stack
Available on all AWS EFA-enabled instances
Limitations:
AWS-only
Software-emulated RDMA writes (higher CPU overhead than true RDMA)
~88% of RoCE RDMA throughput
Documentation: See EFA Transport for build instructions, benchmarks, and tuning.
Advanced Protocols (C++ Transfer Engine)#
The following protocols are available at the C++ Transfer Engine level for specialized use cases. They are not commonly used through the Python API.
NVMe over Fabric (nvmeof)#
Description: Direct data transfer between NVMe storage and DRAM/VRAM using GPUDirect Storage, bypassing the CPU for zero-copy operations.
Use When:
Direct NVMe storage access is needed
Implementing multi-tier storage (DRAM/VRAM/NVMe)
Working with large datasets that don’t fit in memory
Requirements:
NVMe-oF capable storage
Properly mounted remote storage nodes
NVLink (nvlink)#
Description: NVIDIA MNNVL (Multi-Node NVLink) protocol for high-bandwidth, low-latency GPU-to-GPU communication across nodes.
Use When:
Inter-node GPU communication is required
Using NVIDIA MNNVL (Multi-Node NVLink)
Maximum GPU bandwidth is needed
Requirements:
NVIDIA MNNVL hardware
Compiled with
USE_MNNVL=ON
Mooncake Store providers can use this transport for a default-off,
EGM-backed DRAM tier. Configure the Python setup(config) overload with
enable_egm_store_pool=true, protocol="nvlink",
and global_segment_size>0. egm_numa_nodes accepts
auto (the default, using each visible GPU’s CUDA
CU_DEVICE_ATTRIBUTE_HOST_NUMA_ID) or a comma-separated node list. Consumers
do not enable the pool; they use the ordinary nvlink protocol to access the
provider’s mounted segments. Use MC_MS_AUTO_DISC=0 for the manual selection
shown below, for both Providers and Consumers. MC_FORCE_MNNVL is not needed
in this mode. EGM requires a non-TENT Transfer Engine with the nvlink
transport installed.
local_buffer_size controls a separate client staging pool and can be zero
or nonzero. Nonzero buffers use the existing client-buffer allocator, not
the EGM pool allocator. A storage-only Provider can leave it at zero; a
Provider that also uses staging APIs such as put() or get_buffer() needs
a nonzero buffer.
The requested EGM capacity is rounded down to a multiple of the common
alignment: the maximum of the Store slab alignment and the selected nodes’
CUDA allocation granularities. It is distributed across nodes, then split
into balanced, aligned chunks no larger than max_mr_size. This planning
applies only to EGM pools.
Configuration:
# Provider and Consumer: install the requested nvlink transport explicitly.
export MC_MS_AUTO_DISC=0
consumer.setup({
"local_hostname": "10.192.8.58:12400",
"metadata_server": "http://10.192.8.81:8079/metadata",
"master_server_addr": "10.192.8.81:50051",
"protocol": "nvlink",
"global_segment_size": "0",
"local_buffer_size": "0",
"rdma_devices": "",
"enable_egm_store_pool": "false",
})
Note: Manual protocol="nvlink" selection is supported for both Providers
and Consumers. If you use MC_MS_AUTO_DISC=1 instead, set MC_FORCE_MNNVL=1
on hosts with RDMA HCAs so discovery selects MNNVL. EGM setup checks the
actual engine and fails before allocation unless it is non-TENT and has
nvlink installed.
Drain all application and offload calls before closing a Store. Close is
terminal, even on error. EGM cleanup is attempted, and resources whose cleanup
cannot be confirmed are retained until process exit rather than retried by a
later close. See
close() in the Python Store API
for cleanup and failure handling.
Host memory over NVLink (TENT, EGM): on Grace-Blackwell systems the GPUs of
an NVLink domain can also address each other’s host DRAM (Extended GPU Memory).
The TENT mnnvl transport exports host buffers this way when
transports/mnnvl/egm is enabled (MC_MNNVL_EGM=1, off by default), adding the
dram_to_dram and gpu_to_dram capabilities so CPU-resident data (weight or
KV caches) moves over NVLink instead of the NIC:
export MC_ENABLE_MNNVL=1 # select the TENT mnnvl transport
export MC_MNNVL_EGM=1 # transports/mnnvl/egm
Only buffers allocated with allocateLocalMemory("cpu:<numa>") (or any
cuMemCreate allocation with a HOST_NUMA location and a fabric handle) are
exported; other host memory keeps the previous cudaHostRegister behaviour and
is reachable through RDMA/TCP as before. Requires an IMEX domain spanning the
peers and EGM enabled in the driver.
MUSA Transport (musa)#
Description: Moore Threads GPU IPC transport for P2P copies over the intra-node MTLink path. It reuses the NVLink transport’s transfer bookkeeping, but opens imported IPC memory and submits copies using MUSA-specific device context rules.
Requirements:
Moore Threads GPUs with peer access (validated on S5000)
MUSA SDK/runtime; MUSA 5.2 or newer enables the low-CPU transfer-batch API
Compiled with
USE_MUSA=ON
Configuration:
# Use the same runtime-visible logical-device mapping in every peer process.
export MUSA_VISIBLE_DEVICES=0,1
export MC_FORCE_MUSA=1
# Safe defaults shown explicitly. Opt in to metadata after checking the
# visibility contract below; "default" rolls back to per-slice copies.
export MC_MUSA_IPC_OPEN_DEVICE=current
export MC_MUSA_COPY_API=auto
# Performance path after both peers use the same logical device mapping.
export MC_MUSA_IPC_OPEN_DEVICE=metadata
MTHREADS_VISIBLE_DEVICES is consumed by mt-container-toolkit when the
container is created; Mooncake does not use it to infer the MUSA runtime’s
logical device mapping. Buffer metadata uses runtime-visible logical ordinals
such as musa:0. With metadata, every peer must map each logical ordinal to
the same physical GPU. Mooncake validates that the advertised ordinal exists
locally, but it cannot prove cross-peer identity from environment variables.
Both peers must run a version that recognizes the musa protocol; rolling
interoperability with an older peer advertising only nvlink is not supported.
MC_MUSA_IPC_OPEN_DEVICE=current is the safe default; select metadata only
when peers satisfy the logical mapping contract above. Python bindings that
register the default wildcard location (*) resolve the owning MUSA device
during registration; an older peer that still advertises * falls back to the
current-device open path.
In auto mode, batches whose copies are at least 1 MiB use
muMemoryTransferBatchAsync; set MC_MUSA_TRANSFER_BATCH_MIN_BYTES to tune the
threshold, MC_MUSA_COPY_API=transfer_batch to force the API, or
MC_MUSA_COPY_API=default to use the CUDA-compatible per-slice path.
Intra-Node NVLink (nvlink_intra)#
Description: NVIDIA NVLink for GPU-to-GPU communication within a single node.
Use When:
Local GPU-to-GPU transfers are needed
Maximizing intra-node GPU bandwidth
Requirements:
NVIDIA NVLink hardware
Compiled with
USE_INTRA_NVLINK=ON(enabled in the prebuiltx86_64CUDA wheels; other variants must be built from source)Registered buffers must be legacy device allocations (
cudaMalloc/cuMemAlloc), because the transport shares them withcudaIpcGetMemHandle. Virtual-memory allocations (cuMemCreate) have no such handle. In particular, PyTorch tensors allocated withPYTORCH_CUDA_ALLOC_CONF=expandable_segments:Truecannot be registered: allocate the transfer buffers separately, or disableexpandable_segmentsfor them.Peers in containers must share the IPC and PID namespaces, e.g.
docker run --ipc=host --pid=host(Kubernetes:hostIPCplushostPIDorshareProcessNamespace). A CUDA IPC handle carries the exporting process’s PID. Two containers with separate PID namespaces can hand out the same PID, and the importer then rejects the peer’s handle as its own:cudaIpcOpenMemHandle failed: invalid device context. A typical symptom is that only the peer pairs with the same worker index fail.
Configuration:
# Select the intra-node NVLink transport. Cannot be combined with MC_FORCE_MNNVL.
export MC_INTRANODE_NVLINK=true
Note: On a build without USE_MNNVL=ON, leaving MC_INTRANODE_NVLINK unset keeps the usual RDMA (or TCP, when no HCA is detected) selection.
HIP Transport (hip)#
Description: AMD ROCm/HIP transport for GPU communication using IPC handles or Shareable handles.
Use When:
Working with AMD GPUs
Need intra-node GPU communication on AMD hardware
Requirements:
AMD ROCm/HIP runtime
AMD GPUs
Barex Transport (barex)#
Description: Bare-metal RDMA extension protocol for specialized RDMA configurations.
Use When:
Advanced RDMA features are required
Custom RDMA configurations
Requirements:
RDMA-capable hardware
Specialized configuration
CXL Transport (cxl)#
Description: Compute Express Link for memory pooling and sharing across devices.
Use When:
CXL memory pooling is available
Memory disaggregation is needed
Requirements:
CXL-capable hardware
SHM Transport (shm)#
Description: Same-host DRAM copies over POSIX shared memory. Classic Transfer Engine maps the peer’s named shm object, relocates the peer virtual address into the local mapping, and memcpys. This is a first-class transport like HIP, not a replacement for CxlTransport (DAX offset addressing).
Use When:
Two processes on the same machine exchange DRAM buffers
You want to avoid RDMA/TCP loopback for that path
Requirements:
Linux POSIX shm (
/dev/shm), or a writable hugetlbfs mount when allocating withSharedMemoryOptions.use_hugepage(2MB / 512MB / 1GB)Buffers allocated with
TransferEngine::allocateSharedMemory(ordinarymalloccannot be exported)Runtime opt-in:
MC_FORCE_SHM=1, orinstallTransport("shm"). With-DENABLE_MULTI_PROTOCOL=ONthis adds SHM next to RDMA/TCP (rdma,shm/tcp,shm); without it, SHM is the only transport.Same-host SHM and cross-host RDMA/TCP in one engine: build with
-DENABLE_MULTI_PROTOCOL=ON(segment protocol becomesrdma,shmortcp,shm)
Limitations:
Same host only. Without
ENABLE_MULTI_PROTOCOL,MC_FORCE_SHM=1(orinstallTransport("shm")after another transport) setssegment.protocoltoshmand replaces RDMA/TCP routing;installTransport("shm")logs a WARNING when it overwrites a non-empty protocol. Coexistence needs-DENABLE_MULTI_PROTOCOL=ON.registerLocalMemorymust use the pointer fromallocateSharedMemory(a shorter prefix is allowed). A sub-range or overflowing range returns an error instead of silently skipping. Ordinarymallocis still skipped so TCP/RDMA can register it.Same-UID only: objects are created
0600. POSIX names are/mooncake_<pid>_xxxxxxxx; hugepage files are<hugetlbfs-mount>/mooncake_<pid>_xxxxxxxx. Creator and consumer must share a user; a hostname match does not imply a shared/dev/shmor hugetlbfs mount (for example KuberneteshostNetworkpods).Crash or
SIGKILLcan leave POSIX objects in/dev/shmand hugetlbfs files on the mount. There is no automatic reaper (wipingmooncake_*on start would hit live peers on the same mount). POSIX leftovers waste tmpfs until reboot; hugetlbfs leftovers keep hugepages reserved until the file is unlinked or the node reboots. After a crash, delete onlymooncake_<pid>_*whose pid no longer exists, e.g.rm /dev/hugepages/mooncake_<dead-pid>_*.Hugepage allocations do not fall back to tmpfs.
lengthmust be a multiple of the hugepage size; TE does not round up.After
freeSharedMemory+allocateSharedMemory, a peer that still has a cached mapping probes the object name before memcpy. An unlinked object is dropped and the segment descriptor is refetched once; a changed virtual address still requires the initiator to read the newBufferDesc.addr(relocate cannot guess a new offset). Background refresh remains optional viaMC_TE_METADATA_REFRESH_INTERVAL_SECONDS.Relocate caches at most 32 mmap’d peer objects per target. An in-flight copy pins its mapping so prune/cap cannot
munmapit until memcpy returns; the cache may briefly exceed 32 while pins are held.Default off because the path is not NUMA-aware
Mooncake Store segments are not shm-backed until a follow-up allocator change
Ascend Transport (ascend)#
Description: Huawei Ascend NPU communication using HCCL (Huawei Collective Communication Library) or direct transport.
Use When:
Working with Huawei Ascend NPUs
Distributed inference on Ascend hardware
Requirements:
Huawei Ascend NPU hardware
HCCL runtime
Documentation:
Hylink Transport (hylink)#
Description: Transfer Engine transport for Hygon DCU memory over HSL
(Hygon Scale-up Link). HSL connects DCUs directly, including across machines,
and does not use an IB/RoCE NIC. Peers exchange a DTK VMM fabric handle
(hipMemAllocationHandleType 0x8, 512 bytes). The same handle works on one
machine and across machines. An imported fabric address can be granted access
only once, and only to one device, so each local GPU imports and maps the
handle, then grants access on its own device. The TENT transport uses the same
HSL fabric path by default, and remains selectable across machines. Set
MC_HYLINK_USE_VMM=0 on both sides of a TENT run to use HIP IPC in
environments that do not support VMM. IPC cannot cross machines.
Status: Select it with transfer_engine_bench --protocol=hylink.
TENT selects it with transports.hylink.enable=true or
transfer_engine_bench --backend=tent --protocol=hylink. It is off unless
that switch is set, so a DTK build keeps using RDMA/TCP by default.
Use When:
DCU copies on one machine or across machines should use HSL instead of a NIC path. The exporter must register VMM memory (
hipMemCreate)TENT only: set
MC_HYLINK_USE_VMM=0in environments that do not support VMM. That path uses same-machinehipMallocbuffers and a HIP IPC handle, and cannot cross machines
Requirements:
Built with
-DUSE_HYLINK=ON(impliesUSE_HIP)TENT builds also pass
-DUSE_TENT=ONHygon DTK runtime
Both sides must support DTK VMM fabric
TENT IPC does not require VMM and stays on one machine
TPU Transport (tpu) — Experimental#
Description: Google TPU support in the TENT runtime. Because TPU HBM is not
directly addressable by the NIC, transfers touching TPU memory are staged
through host DRAM: the HBM ↔ host-DRAM hop is performed by a PJRT device-copy
adapter, and the host ↔ host hop is carried by an existing transport (RDMA/TCP).
The two stages are chained automatically by the TENT staging pipeline
(ProxyManager), so no separate networked TPU transport is required.
Status: Experimental. The C++/TENT data path is gated behind -DUSE_TPU=ON
(OFF by default). A serving-framework (JAX / PyTorch-XLA) integration layer is
planned as a follow-up.
Use When:
Disaggregated prefill/decode serving on TPU hosts
KV-cache transfer between TPU nodes over RDMA/TCP
Requirements:
Built with
-DUSE_TPU=ON -DUSE_TENT=ONA PJRT device-copy adapter shared library exposing the
mc_tpu_pjrt_*C ABI (seetpu_pjrt_abi.h). The adapter is resolved at runtime viadlopen; its path defaults tolibmooncake_tpu_pjrt.soand can be overridden with theMC_TPU_PJRT_LIBenvironment variable. No PJRT/TPU SDK is required at build time.An RDMA (or TCP) transport enabled for the host ↔ host hop.
Design notes:
TPU memory is reported as a distinct memory type (
tpu:Nlocations); the staging policy routes the local HBM ↔ host copy to the TPU device-copy transport and the cross-node hop to RDMA/TCP.DMA-mapped (pinned) staging buffers for true async device DMA are a planned performance follow-up.
Intel XPU Transport (xpu)#
Description: Intel GPU support in TENT through oneAPI SYCL. On the same
node, the XPU transport copies between XPUs. Within a process, the copy runs
directly over PCIe (or Xe Link) when the two devices have peer access, and is
bounced through host memory otherwise. Between processes, it maps the peer’s
buffer through a Level Zero IPC handle when the IPC requirements below are met.
With rdma, registered XPU memory is accessed directly through dma-buf when
available. Otherwise, the XPU transport performs the local device-to-host and
host-to-device copies, and an existing TCP/RDMA transport carries the staged
data between peers. See the Intel XPU notes in the RDMA section above.
Status: TENT only. xpu is a local transport (host staging and same-node
XPU copies), not a network protocol to pass to Store setup. Select tcp or
rdma for the network hop.
Use When:
Moving Intel GPU device buffers through TENT
Copying between Intel GPUs on one node, including between processes such as prefill and decode workers
Reading and writing PyTorch XPU tensors with the C++ Mooncake Store backend
Requirements:
Built with
-DUSE_XPU=ON -DUSE_TENT=ONusing the Intel oneAPI compilers (icpxfor C++ is required; the build examples also useicxfor C)Compatible SYCL and Level Zero runtimes and access to the Intel GPU
MC_USE_TENT=1before constructing the Store client or compatibility API engineA TCP or RDMA transport for transfers between nodes, or when same-node IPC is unavailable
Configuration:
export ONEAPI_DEVICE_SELECTOR=level_zero:gpu
export MC_USE_TENT=1
Design notes:
Device memory uses
xpu:Nlocations. Host/shared USM is treated as host memory.PyTorch XPU device pointers are recognized through the platform default SYCL context. Synchronize producing work before passing a buffer to Mooncake, and keep registered allocations alive until transfers complete.
Same-node IPC is used only when the selector policy allows
xpu; a policy with a non-emptytransportslist must name"xpu"ahead of"rdma"(see Transport Selector). Settransports/xpu/disable_ipctotrueto turn IPC off.
Limitations:
No XPU support in the classic Transfer Engine
Transfers involving XPU memory require an XPU-platform initiator (see the RDMA section above)
Same-node IPC between processes requires both processes in the same PID namespace, peer access from the copying device to the device that holds the buffer, and ptrace permission over the exporting process: Yama
ptrace_scope0 or 1, orCAP_SYS_PTRACEfor scope 2; scope 3 rejects the import even with that capability. Otherwise the transfer takes the network path (RDMA dma-buf or host staging); see the GPU-Direct note in the build guide.
Build instructions: See Build with Intel XPU.
MPComm Transport (mpcomm)#
Description: UCL-MPComm (Unified Communication Library - Memory Pool Communication) is an RDMA library for heterogeneous memory pooling, integrated as a TENT transport. It drives multiple RDMA NICs concurrently with two-level load balancing (across NICs, and across QPs within a NIC) and NUMA-aware worker placement, exposing one-sided put/get primitives. It is shortened to MPComm below.
Status: TENT only. There is no MPComm backend on the legacy Transfer Engine transport path,
so it cannot be selected through MOONCAKE_PROTOCOL or transfer_engine_bench --protocol=.
Use When:
The host has several RDMA NICs and you want them saturated by a single transfer stream
Multi-NUMA hosts where NIC-to-NUMA affinity matters
Requirements:
Built with
-DUSE_TENT=ON -DUSE_MPCOMM=ON -DMPCOMM_ROOT=<prefix>MPComm installed, providing
include/mpcomm.handlib/libmpcomm.so(Tencent/UCL-MPComm)libmpcomm.soreachable by the dynamic linker at run time
Enable:
{ "transports": { "mpcomm": { "enable": true } } }
See MPComm Transport for the full guide, including selection via transport policy, tuning environment variables, and troubleshooting.
FlagOS FlagCX Transport (flagcx)#
Description: FlagCX is the unified communication library in the FlagOS ecosystem for multi-vendor and cross-vendor deployments. Mooncake integrates the FlagCX P2P Engine as a classic Transfer Engine transport, allowing the existing Mooncake transfer workflow to use the accelerator and network backends provided by the local FlagCX build.
Use When:
Deploying Mooncake on a platform supported by FlagCX
Using FlagCX’s P2P Engine for accelerator memory transfers
Building a cross-vendor deployment around the FlagOS communication stack
Build Requirements:
cmake -S . -B build \
-DUSE_FLAGCX=ON \
-DFLAGCX_HOME=/path/to/FlagCX/build
cmake --build build -j
FLAGCX_HOME must contain include/flagcx_p2p.h and either lib/libflagcx.so or
lib64/libflagcx.so. If it is omitted, Mooncake checks $FLAGCX_HOME and then
$HOME/FlagCX/build.
Configuration:
engine.initialize(
hostname="node1",
metadata_server="P2PHANDSHAKE",
protocol="flagcx",
device_name=""
)
# Select the interface used for FlagCX bootstrap and endpoint advertisement.
export FLAGCX_SOCKET_IFNAME="eth0"
Current Scope:
Available through the classic Transfer Engine; it is not a TENT transport
Must be built from source with
USE_FLAGCX=ONShould be selected as the standalone
flagcxprotocol, not as part of a multi-protocol stringBuffers should be registered before the first transfer to a peer and remain registered while that peer connection is active
See FlagOS FlagCX Transport for dependency, build, benchmark, runtime configuration, and troubleshooting details.
Configuration Examples#
Configuration File (JSON)#
TCP Configuration:
{
"local_hostname": "localhost",
"metadata_server": "localhost:8080",
"protocol": "tcp",
"device_name": "",
"master_server_address": "localhost:8081"
}
RDMA Configuration:
{
"local_hostname": "node1",
"metadata_server": "etcd://10.0.0.1:2379",
"global_segment_size": "3GB",
"local_buffer_size": "1GB",
"protocol": "rdma",
"device_name": "mlx5_0",
"master_server_address": "10.0.0.1:8081"
}
Environment Variables#
# TCP (Default)
export MOONCAKE_PROTOCOL="tcp"
# RDMA with specific device
export MOONCAKE_PROTOCOL="rdma"
export MOONCAKE_DEVICE="mlx5_0"
# RDMA with auto-discovery
export MOONCAKE_PROTOCOL="rdma"
export MOONCAKE_DEVICE="auto-discovery"
# Other configuration
export MOONCAKE_MASTER="10.0.0.1:50051"
export MOONCAKE_TE_META_DATA_SERVER="P2PHANDSHAKE"
export MOONCAKE_LOCAL_HOSTNAME="node1"
Choosing the Right Protocol#
Scenario |
Recommended Protocol |
Notes |
|---|---|---|
Development/Testing |
tcp |
Simple setup, no special hardware |
Production Inference |
rdma |
Best performance and latency |
AWS Cloud (EFA instances) |
efa |
High performance on p5e, p6-b200, p4d, etc. |
Cloud Environments |
tcp or rdma (if available) |
Check cloud provider support |
Multi-tier Storage |
rdma + nvmeof |
Combine protocols for different layers |
AMD GPU Clusters |
rdma + hip |
Use HIP for local GPU communication |
Cambricon MLU Clusters |
rdma |
Build with |
Intel XPU Clusters |
tcp or rdma (TENT) |
Build with |
Ascend NPU Clusters |
rdma + ascend |
Use Ascend for NPU-specific operations |
Hygon DCU Clusters |
rdma + hylink |
Build with |
Multi-vendor or cross-vendor clusters |
flagcx |
Build with |
Troubleshooting#
RDMA Connection Issues#
Check RDMA devices:
ibv_devices ibv_devinfo
Verify network connectivity:
# Test RDMA connectivity (requires rdma-core tools) rping -s # On server rping -c -a <server_ip> -v # On client
Check permissions:
RDMA may require elevated permissions
Run with
sudoif necessaryConfigure proper udev rules for non-root access
Firewall configuration:
Ensure RDMA ports are not blocked
Check InfiniBand subnet manager is running
Protocol Selection#
If a protocol fails to initialize:
Verify hardware support
Check that required drivers are installed
Ensure compile-time flags are set correctly (for C++ protocols)
Fall back to TCP for basic functionality
See Also#
Quick Start - Start with Mooncake integrations for serving frameworks
Transfer Engine Design - Detailed architecture
Transfer Engine Benchmark - Performance tuning
Python API Reference - API documentation
Deployment Guide - Production deployment